Zhangxi Tan

I am a leading expert and serial entrepreneur in the global RISC-V community. Serving as the chief architect, I led many commercial industry RISC-V microprocessor tapeouts in advanced technologies with several foundries.

University of California, Berkeley

Postdoc Researcher in the ASPIRE lab                                        2013

University of California, Berkeley

PhD in Computer Science, minor in Management of Technology              2008 – 2013

Advisor: Prof. David A. Patterson

University of California, Berkeley                                      2005 – 2008

Master in Computer Science

Advisor: Prof. David A. Patterson

Tsinghua University, China                                            2002 – 2005

Master in Computer Science  

Tsinghua University, China                                            1998 – 2002

Bachelor in Electronics Engineering 

Tsinghua Shenzhen International Graduate School                           2023 - Now

Adjunct Associate Professor

Co-Director，RISC-V International Open-Source Laboratory (RIOS)

Tsinghua-Berkeley Shenzhen Institute, Shenzhen                          2018 - 2023

Adjunct Assistant Professor

Co-Director，RISC-V International Open-Source Laboratory (RIOS)

RIVAI Technologies (Shenzhen) Co., Ltd.                                 2018 - Now

Founder and CEO

Backed by notable VC firms

OURS Technology Inc.                                                2017 - 2021

Founder and CEO

Acquired by Aurora Innovation, NASDAQ: AUR

Pure Storage (NYSE: PSTG)                                           2013 - 2017

Founding Engineer

Lead designer/architect of FlashBlade generating more than $1B revenue yearly

· Board Member, RISC-V International                                                                       2020 - 2023                                                                  

· Technical Steering Committee, RISC-V International                                                2020 - Now   

RESEARCH AREA

My primary research is computer architecture and networks, microprocessor and VLSI designs, open-source RISC-V technologies and ecosystems, OpenEDA and PDK, non-volatile memory systems, SW/HW co-design, implementation of computer systems and generative AI on chip designs.

RESEARCH FUNDINGS

Total external funding as PI or Co-PI: ¥ 105M, from Shenzhen Innovation fund (for RIOS) as well as notable industry companies, such as Analog Devices, Bytedance, Intel, Imagination, and ASR Microelectronics.

Supervised Chip Design Competition Awards

Xinze Wang, Guohua Yin, Yifei Zhu, CyberRio:  the world’s first RISC-V CPU designed using LLM, Efabless AI Generated Open-Source Silicon Design Challenge, June 2023 (the 2nd place winner)

Yihai Zhang, GreenRio 2: A Linux-compatible RISC-V Processor Developed with A Fully Open-Source EDA Flow, the 1st place in the code-a-chip design competition, International Solid-State Circuits Conference (ISSCC-2023), San Francisco, CA, February 2023 

Readings in Computer Systems, TBSI, 2020-2023

Advanced Micro Processor Processor Design, TBSI, 2020-2023

SELECTED PUBLICATIONS

Derek Tu, Zhangxi Tan, RGen: A Tool for Generating Compiler, Simulator, and Application Support, Workshop on Computer Architecture Research with RISC-V (CARRV) , 2023 International Symposium on Computer Architecture (ISCA-2023), Orlando, FL, June 2023

Ye Cao, Zhixuan Xu, Zhangxi Tan, QEMU-CAS: A Full-System Cycle-Accurate Simulation Framework based on QEMU, Cache Coherent Framework for RISC-V Many-core Systems, Workshop on Computer Architecture Research with RISC-V (CARRV) , 2023 International Symposium on Computer Architecture (ISCA-2023), Orlando, FL, June 2023

Zexin Fu, Mingzi Wang, Yihai Zhang, Zhangxi Tan, Cache Coherent Framework for RISC-V Many-core Systems, Workshop on Computer Architecture Research with RISC-V (CARRV) , 2023 International Symposium on Computer Architecture (ISCA-2023), Orlando, FL, June 2023

Yifei Zhu, Xinze Wang, Guohua Yin, Yihai Zhang, Zhengxuan Luan, Mingzi Wang, Peichen Guo, Xinlai Wan, Shenwei Hu, Dongyu Zhang, Qiaowen Yang, Zhangxi Tan, GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations, RISC-V Summit Europe, Barcelona, June 2023

Shenwei Hu, Xi Wang, Zhangxi Tan, Automatic Test Generation and Verification for RISC-V Vector Extension, RISC-V Global Summit, Santa Clara, CA, December 2022

Yifei Zhu, Guohua Yin, Xinze Wang, Qiaowen Yang, Zhengxuan Luan, Yihai Zhang, Mingzi Wang, Peichen Guo, Xinlai Wan, Shenwei Hu, Dongyu Zhang, Yucheng Wang, WeiWei Chen, Lei Ren, Zhangxi Tan, GreenRio: A Modern RISC-V Microprocessor Completely Designed with An Agile Open-source EDA Flow, Workshop on Open-Source EDA Technology (WOSET) by International Conference on Computer-Aided Design（ICCAD-2022), San Diego, CA, November 2022

- Also appeared in a talk at RISC-V Day Japan, Yokohoma , November 2022

Zhangxi Tan, Lin Zhang, David Patterson, Yi Li, PicoRio: An Open-Source, RISC-V Small-Board Computer to Elevate the RISC-V Software Ecosystem, Tsinghua Science and Technology, June 2021, 26(3): 384–386

Zhangxi Tan, PicoRio: An Open-Source, RISC-V Small-Board Computer To Elevate The RISC-V Software Ecosystem, RISC-V Global Forum 2020, September 2020

Zhangxi Tan, Zhenghao Qian, Xi Chen, Krste Asanovic, David Patterson, DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs, 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2015), Istanbul, Turkey, March 2015

Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David Patterson, A Case for FAME: FPGA Architecture Model Execution, International Symposium on Computer Architecture (ISCA-2010), Saint-Malo, France, June 2010

Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David Patterson, Krste Asanovic, RAMP Gold: An FPGA-based Architecture Simulator for Multiprocessors, in 47th Design Automation Conference (DAC'10), Anaheim, CA, June 2010

Jonathan Ellithorpe, Zhangxi Tan, Randy Katz, Internet-in-a-Box: emulating data center network architectures using FPGAs, in 46th Design Automation Conference (DAC'09), Association for Computing Machinery, Inc., June 2009

John Davis, Zhangxi Tan, Fang Yu, and Lintao Zhang, A Practical Reconfigurable Hardware Accelerator for Boolean Satisfiability Solvers, in 45th Design Automation Conference (DAC'08), Association for Computing Machinery, Inc., June 2008

John D. Davis, Zhangxi Tan, Fang Yu, and Lintao Zhang, Designing an Efficient Hardware Implication Accelerator for SAT Solving, in International Conference on Theory and Applications of Satisfiability Testing (SAT'08), Springer, Guangzhou, China, May 2008

PATENT

Dr. Tan holds more than 30 US patents in professional fields such as microprocessor designs, hardware accelerators and flash memory systems.