RISC-V Mentorship Program Summer 2022 Session

Summer Term: June 1st – August 31st, 2022


The RISC-V Mentorship Program enables one or more internship-style projects per 12-week session which match mentors and project leaders together with mentees and interns. Mentees are guided through a series of milestones by one or more project mentors through their project work and weekly meetings.


Tsinghua-Berkeley RISC-V International Open Source Laboratory, as a Premier Members of the RISC-V International, also officially joined the RISC-V Mentorship Program, and will lead students to complete the RVV Random Test Generation.


Benefits for Mentees

· Official Summer Practice Certificate

· Gain exposure to real-world ISA and hardware development practices by working closely with experienced developers in the community.

· Learn best practices of working within open source development infrastructure, tooling, and culture.

· Build experience through hands-on work related to academic and professional interests.

· Cultivate close working relationships with RISC-V experts and industry leaders to expand professional network.

· Receive a stipend from the sponsoring organization based on project criteria.


Project Random Test Generation for RISC-V Vector Extension

TimeJune 1st – August 31st, 2022

LocationOnline/Offline (E-mail notification)


Following the ratification of RVV specification, the software simulation framework and RTL designs for RVV have been released. Given the complexity of RVV design and the combinations of its configuration, both developers and users need a golden test suite to verify the correctness of the respective RVV implementations and simulations.


RIOS lab thus introduces this project and contributes to RISC-V foundation. In this project, you will be designing a RVV test generator to help verify the functionality of either simulator or ASIC design of RISC-V vector processors. This project has two phases. In the first phase, we will write the a constant test suite generator for RVV that automatically produces the same test streams given a fixed RVV configuration. This would help debug and ensure reproducibility needed by developers. While in phase 2, we will extend the test generator to produce random vector test to cover the corner case of the RVV design.


RVV Spec: https://github.com/riscv/riscv-v-spec

RISC-V CTG: https://github.com/riscv-software-src/riscv-ctg

RISCOF: https://github.com/riscv-software-src/riscof

RISCOF Documentation: https://riscof.readthedocs.io/en/latest/intro.html


Learning Objectives:

1. RVV instruction set architecture

2. How does vector processor work?

3. Formal Verification of RVV

4. Test generation and verification model

5. Design of advanced random test generation framework



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· Applications open: April 14 – May 16 (4 weeks)

· Application review/admission decisions/HR paperwork: May 17 – May 31, 2022


Other Projects

In addition, there are also opportunities to participate in multiple projects jointly created by RIOS Lab. If you are interested in the following projects, you can send an email (named with name + project) to info@rioslab.org and contact us.


RISC-V Small Computer PicoRio

the first Linux-capable RISC-V small board computer: PicoRio.



RISC-V Chrome OS Support

RIOS Lab completed Chrome OS prebuilt tarballContributed over 200 commits to the official Gentoo Linux repository.



RVV Sail Model

RISC-V Vector (RVV) is a RISCV Vector ISA extensionprovides RISC-V vectorization support.



RISC-V Binary Translation

RIOS will provide an open-source binary translation solutionallowing RISC-V CPUs to execute applications of x86 and ARM.


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